CSE211 Practice MCQS 100+

1. Register A:1100 Register B:1010 After applying Selective-Set on the given data, value of register A is:

   1. 1001
   2. 1110
   3. 1011
   4. 1111
   Answer :     Option ( b )

2. A digital system has a common bus system for 16 registers of 32 bits each. If the bus constructed using multiplexers, then how many multiplexers are there in the bus?

   1. 8
   2. 16
   3. 32
   4. 64
   Answer :     Option ( c )

3. Mask logic micro-operation implements which of the following logic gate?

   1. OR
   2. AND
   3. XOR
   4. NAND
   Answer :     Option ( b )

4. Binary adder is constructed using?

   1. 4 bit Adder
   2. Half adder
   3. Full adder
   4. Sequential circuit
   Answer :     Option ( c )

5. What is the effect on the output if ashl operation is performed?

   1. Subtraction by 2
   2. Multiplication by 2
   3. Division by 2
   4. Subtraction by 2
   Answer :     Option ( b )

6. What is the output in 3-state bus buffer if the input c=0?

   1. 0
   2. 1
   3. Buffer
   4. High Impedance
   Answer :     Option ( d )

7. If the values of two inputs in Half-Adder are1 and 1, then outputs (Carry and Sum) will have values respectively:

   1. C=1, S=1
   2. C=1,S=0
   3. C=0,S=1
   4. C=0,S=0
   Answer :     Option ( b )

8. The number of bits in the opcode are dependent on:

   1. Total number of words
   2. Number of bits in a word
   3. Total number of addresses
   4. Total number of operations
   Answer :     Option ( d )

9. Which input should be enabled for any register to accept some data?

   1. LD
   2. INR
   3. CLR
   4. DEC
   Answer :     Option ( a )

10. A group of bits that instructs the computer to perform a specific operation is known as:

    1. Instruction Code
    2. Operation Code
    3. Addressing Mode
    4. None
    Answer :     Option ( b )

11. Which type of instruction is represented by the op-code 0111?

    1. Memory Reference Instruction
    2. Register Reference Instruction
    3. Input-Output Instruction
    4. None of These
    Answer :     Option ( b )

12. Which register is used to store the results of any operation?

    1. AR
    2. AC
    3. TR
    4. DR
    Answer :     Option ( b )

13. By what timing signal the Memory-Reference Instructions are executed?

    1. T3
    2. T4
    3. T2
    4. T5
    Answer :     Option ( b )

14. STA is which type of instruction?

    1. Register Reference
    2. Memory Reference
    3. Input-Output
    4. None
    Answer :     Option ( b )

15. Identify the Register-Reference Instruction.

    1. Exxx
    2. F182
    3. 7642
    4. Axxx
    Answer :     Option ( b )

16. In which of the following addressing modes, the immediate operand is included in the instruction itself?

    1. Register Mode
    2. Immediate Mode
    3. Base Register Addressing Mode
    4. None
    Answer :     Option ( b )

17. DD R1,A,B is which type of instruction?

    1. Zero Address Instruction
    2. One Address Instruction
    3. Two address Instruction
    4. Three Address Instruction
    Answer :     Option ( d )

18. Which among these is not a Data Transfer Instruction?

    1. Exchange
    2. Pop
    3. Negate
    4. Input
    Answer :     Option ( c )

19. A computer with large number of instructions is classified as:

    1. RISC
    2. CISC
    3. Pipeline
    4. None
    Answer :     Option ( b )

20. Which of the following instruction is not a Logical Instruction ?

    1. Clear
    2. Enable Interrupt
    3. Multiply
    4. OR
    Answer :     Option ( c )

21. Internal Interrupts are also known as:

    1. Software Interrupt
    2. Traps
    3. Pop
    4. None
    Answer :     Option ( b )

22. Which is true for Indirect Address Mode ?

    1. Effective Address = Address part of Instruction
    2. Effective Address = EA + PC
    3. Effective Address = Relative Address
    4. Effective Address = Address part of Instruction + Content of CPU register
    Answer :     Option ( d )

23. Among the following instructions, which instruction is odd one out?

    1. Jump
    2. Return
    3. Rotate left
    4. Compare
    Answer :     Option ( c )

24. In memory read the operation puts memory address on to a register known as :

    1. PC
    2. ALU
    3. MAR
    4. All of these
    Answer :     Option ( c )

25. In 3 state gate third position termed as high impedance state which acts as:

    1. Open circuit
    2. Close circuit
    3. None of these
    4. All of above
    Answer :     Option ( a )

26. How is the effective address of base-register calculated?

    1. By addition of index register contents to the partial address in instruction
    2. By addition of implied register contents to the partial address in instruction
    3. By addition of PC register contents to the complete address in instruction
    4. By addition of implied register contents to the complete address in instruction
    Answer :     Option ( a )

27. Shift left is equal to:

    1. multiply by two
    2. add by two
    3. divide by two
    4. subtract by two
    Answer :     Option ( a )

28. Which register holds the address for a stack whose value is supposed to be directed at the topmost position?

    1. Stack Pointer
    2. Stack Register
    3. Both a & b
    4. None of the above
    Answer :     Option ( a )

29. In which of these addressing modes, a constant is specified in the instruction, after the opcode byte?

    1. register instructions
    2. register specific instructions
    3. direct addressing
    4. immediate mode
    Answer :     Option ( d )

30. The contents of the program counter is the _______ of the instruction to be run:

    1. Data
    2. Address
    3. Counter
    4. None of these
    Answer :     Option ( b )

31. The return address of the Sub-routine is pointed to by _______

    1. IR
    2. PC
    3. MAR
    4. Special memory registers
    Answer :     Option ( b )

32. In the case of, Zero-address instruction method the operands are stored in _____

    1. Registers
    2. Accumulators
    3. Push down stack
    4. Cache
    Answer :     Option ( c )

33. The addressing mode which makes use of in direction pointers is ______

    1. Indirect addressing mode
    2. Index addressing mode
    3. Relative addressing mode
    4. Offset addressing mode
    Answer :     Option ( a )

34. The computer architecture aimed at reducing the time of execution of instructions is ________

    1. CISC
    2. RISC
    3. ISA
    4. ANNA
    Answer :     Option ( b )

35. The addressing mode, where you directly specify the operand value is _______

    1. Immediate
    2. Direct
    3. Definite
    4. Relative
    Answer :     Option ( a )

36. The circuit used to store one bit of data is known as

    1. Register
    2. Encoder
    3. Decoder
    4. Flip Flop
    Answer :     Option ( d )

37. The load instruction is mostly used to designate a transfer from memory to a processor register known as

    1. Accumulator
    2. Instruction Register
    3. Program counter
    4. Memory address Register
    Answer :     Option ( a )

38. Which are stages of instruction cycle:

    1. Fetch
    2. Decode,Execute
    3. Derive effective address of the instruction
    4. All of these
    Answer :     Option ( d )

39. A circuit which performs the conversion from binary data to decimal is called as________.

    1. Encoder
    2. Multiplexer
    3. Decoder
    4. Code Converter
    Answer :     Option ( d )

40. A digital circuit which is used to store a single bit is

    1. Encoder
    2. OR gate
    3. Flip Flop
    4. Decoder
    Answer :     Option ( c )

41. Which is the major functioning responsibility of the multiplexing combinational circuit?

    1. Decoding the binary information
    2. Generation of all minterms in an output function with OR-gate
    3. Generation of selected path between multiple sources and a single destination
    4. Encoding of binary information
    Answer :     Option ( c )

42. What is the function of an enable input on a multiplexer chip?

    1. To apply Vcc
    2. To connect ground
    3. To active the entire chip
    4. To active one half of the chip
    Answer :     Option ( c )

43. One multiplexer can take the place of ___________

    1. Several SSI logic gates
    2. Combinational logic circuits
    3. Several Ex-NOR gates
    4. Several SSI logic gates or combinational logic circuits
    Answer :     Option ( d )

44. In a multiplexer, the selection of a particular input line is controlled by ___________

    1. Data controller
    2. Selected lines
    3. Logic gates
    4. Both data controller and selected lines
    Answer :     Option ( b )

45. If the number of input lines is equal to `2^m` then it requires _____ select lines.

    1. 2
    2. m
    3. n
    4. 2n
    Answer :     Option ( b )

46. How many select lines would be required for an 8-line-to-1-line multiplexer?

    1. 2
    2. 4
    3. 8
    4. 3
    Answer :     Option ( d )

47. A basic multiplexer principle can be demonstrated through the use of a ___________

    1. Single-pole relay
    2. DPDT switch
    3. Rotary switch
    4. Linear stepper
    Answer :     Option ( c )

48. The enable input is also known as __________

    1. Select input
    2. Decoded input
    3. Strobe
    4. Sink
    Answer :     Option ( c )

49. If we record any music in any recorder, such types of process is called ______

    1. Multiplexing
    2. Encoding
    3. Decoding
    4. Demultiplexing
    Answer :     Option ( b )

50. For 8-bit input encoder how many combinations are possible?

    1. `8`
    2. `2^8`
    3. `4`
    4. `2^4`
    Answer :     Option ( b )

51. Subtraction in Computer is performed by

    1. 1's Complement method
    2. 2's complement method
    3. Signed magnitude method
    4. BCD subtraction method
    Answer :     Option ( b )

52. A sequence or group of bits, which tells the computer to perform a specific operation is called as

    1. Instruction Code
    2. Micro-operation
    3. Accumulator
    4. Register
    Answer :     Option ( a )

53. A load instruction in a computer, transfer the data of the given memory address to which of the processor Register?

    1. Instruction Register
    2. Program counter
    3. Memory Address Register
    4. Accumulator
    Answer :     Option ( d )

54. The components of processor in computer, communicates using_____ & ______

    1. Address Bus & Data Bus
    2. I/O Bus & Control Bus
    3. Serial input Bus & Serial Output Bus
    4. Interrupt Bus & Control Bus
    Answer :     Option ( a )

55. Which one of the following statement in relation to the microprogram sequencer is true

    1. It generates the control signal to execute a micro instruction
    2. It sequences the micro instructions in the control memory
    3. it generates the address of next micro instruction to be executed
    4. Enables the efficient handling of a micro program subroutine
    Answer :     Option ( c )

56. The main memory in a computing system is made up of

    1. Cache memory
    2. Static RAM
    3. Dynamic RAM
    4. Both (A) and (B)
    Answer :     Option ( d )

57. An assembly language

    1. Uses alphabetic codes in place of binary numbers used in machine language
    2. Need not be translated into machine language
    3. is the easiest language to write programs
    4. All of the above
    Answer :     Option ( a )

58. Pipelining technique increases the CPU throughput at the same time it reduces

    1. Terminating time
    2. Resuming time
    3. Controlling time
    4. Execution time
    Answer :     Option ( d )

59. Consider the following sequence of instructions DADD R1, R2, R3 DSUB R4, R1, R5 AND R6, R1, R7 OR R8, R1, R9 XOR R10, R1, R11 The last three instructions uses the result of the following instruction/s.

    1. AND instruction
    2. DADD instruction
    3. DSUB instruction
    4. XOR Instruction
    Answer :     Option ( b )

60. Alternate name for pipeline process is

    1. Stall interlock
    2. Stall deadlock
    3. Assembly line operation
    4. Pipeline interlock
    Answer :     Option ( c )

61. Which one of the merit is achieved due to pipelining

    1. optimizing the compilers
    2. speed up utilities
    3. improving software
    4. all of the above
    Answer :     Option ( d )

62. Pipelining technique increases the

    1. Cycle rate
    2. time
    3. size
    4. through put
    Answer :     Option ( d )

63. The process of letting an instruction move from decode stage into the execution stage of pipeline is usually called as

    1. nullifying
    2. branch prediction
    3. instruction issue
    4. canceling
    Answer :     Option ( c )

64. Which of the following registers keeps track of the instructions, stored in program memory.

    1. AR (Address Register)
    2. XR (Index Register)
    3. PC (Program Counter)
    4. AC (Accumulator)
    Answer :     Option ( c )

65. RAM is an acronym of

    1. Random Access Memory
    2. Random Origin Memory
    3. Random Only Memory
    4. Repeated Access Memory
    Answer :     Option ( a )

66. Which one of the following is/are the components of CPU

    1. Storage component
    2. Execution component
    3. Transfer component
    4. All of the above
    Answer :     Option ( d )

67. in a computer processor, multiple registers is/are connected to ALU using

    1. Multiplexers
    2. Buses
    3. decoders
    4. Both a & b
    Answer :     Option ( d )

68. A group of bits consisting of selecting bits of multiplexers, decoder and the operation code is called as

    1. Control word
    2. Memory word
    3. Program word
    4. Arithmetic Word
    Answer :     Option ( a )

69. Register Stack Organization in CPU is suitable for

    1. Subroutine operations
    2. Nested Subroutine & loop operations
    3. Interupt operations
    4. All of the above
    Answer :     Option ( b )

70. Register Stack organization in a cpu is a

    1. FIFO
    2. FILO
    3. LIFO
    4. LILO
    Answer :     Option ( c )

71. In a register Stack organization _________ operation is/are supported

    1. PUSH
    2. POP
    3. Both a & b
    4. PULL
    Answer :     Option ( c)

72. In memory stack organization of a cpu the PUSH & POP instructions, ____&____ the stack pointer

    1. Increments, decrements
    2. increments, increments
    3. decrments, decrements
    4. decrements, increments
    Answer :     Option ( d )

73. Which one of the following best identifies an infix representation of a microoperation

    1. A + B
    2. + A B
    3. A B+
    4. All a,b,c
    Answer :     Option ( a )

74. Which one of the following best identifies a polish representation of a microoperation A added with B.

    1. A + B
    2. + A B
    3. A B+
    4. All a,b,c
    Answer :     Option ( b )

75. Identify which of the following is a three address instruction/s

    1. ADD R1, A, B
    2. ADD R2, C, D
    3. MUL X, R1, R2
    4. All of the Above
    Answer :     Option ( d )

76. Is there any zero address instructions in a computer

    1. YES
    2. No
    Answer :     Option ( a )

77. RISC stands for

    1. Remaining Instruction Set of Computer
    2. Reduced Instruction Set Computer
    3. Remaining intermediate storage of Computer
    4. Reduced intermediate storage of computer
    Answer :     Option ( b )

78. The CISC stands for ______

    1. Computer Indexed Set Components
    2. Computer Instruction Set Compliment
    3. Complex Instruction set computer
    4. Complete Instruction Set Compliment
    Answer :     Option ( c )

79. The RISC processor has a more complicated design than CISC.

    1. True
    2. False
    Answer :     Option ( b )

80. Pipe-lining is a unique feature of _______

    1. RISC
    2. CISC
    3. ISA
    4. IANA
    Answer :     Option ( a )

81. A memory manamgement technique in which system stores and retrieves data from secondary storage for use in main memory is called

    1. Paging
    2. mapping
    3. Fragmentation
    4. pipelining
    Answer :     Option ( a )

82. An instruction level pipelining in CPU is achieved by using

    1. Stack
    2. LIFO Buffer
    3. FIFO Buffer
    4. None of the above
    Answer :     Option ( c )

83. Which one of the following instruction is a direct addressing mode

    1. LD 2300h
    2. MOV R2, R1
    3. CMP R3
    4. CMA
    Answer :     Option ( a )

84. Which one of the following instruction is a immediate addressing mode

    1. ST 2500h
    2. MOV R2, R3
    3. ADD R6
    4. MVI R2, #data
    Answer :     Option ( d )

85. Identify which one of the following instruction is not a Logical/Bit manipulation category

    1. CLR
    2. COM
    3. CLRC
    4. ADD R5
    Answer :     Option ( d )

86. The instruction ROR means

    1. Rotate right with carry
    2. Rotate right without carry
    3. rotate right with zero
    4. Rotate roght with Sign
    Answer :     Option ( b )

87. The EI (Enable interrupt) & DI (Disable Interrupt) are bit manipulation instructions of CPU

    1. True
    2. False
    Answer :     Option ( a )

88. The instructions namely INC, DEC, NEG, ADDC are all__________ instructions

    1. Logical
    2. Shift
    3. Arithmetic
    4. Bit manipulation
    Answer :     Option ( c )

89. The location for storing the return address in a subroutine is

    1. Fixed location in main memory
    2. In a processor Register
    3. In a memory Stack
    4. All of the above
    Answer :     Option ( d )

90. When divide by zero occurs, then the type of interrupt happens is

    1. External interrupt
    2. Internal Interrupt
    3. Software interrupt
    4. None of the above
    Answer :     Option ( b )

91. Which one of the following is a external interrupt type

    1. Power failure
    2. I/O device data Transfer
    3. Register Overflow
    4. Both a & b
    Answer :     Option ( d )

92. How do we classify the interrupt happening due to op-code violation?

    1. External interrupt
    2. Internal interrupt
    3. Software interrupt
    4. None of the above
    Answer :     Option ( b )

93. External and Internal interrupts are initiated by the

    1. Hardware
    2. Software
    3. Firmware
    4. execution of an instruction
    Answer :     Option ( a )

94. An interupt is happening due to execution of an instruction , then it is

    1. Hardware interrupt
    2. Software interrupt
    3. internal interrupt
    4. No interrupt
    Answer :     Option ( b )

95. Characteristics of CISC is

    1. Large set of instructions
    2. Many addressing modes
    3. Variable length instruction
    4. All of the above
    Answer :     Option ( d )

96. Select the correct sequence of operation in CPU

    1. Instruction Fetch, instruction decode, Operand fetch, instruction execute, operand store
    2. Instruction decode, operand fetch, instruction execute, instruction fetch, operand store
    3. Instruction fetch, operand fetch, instriction decode, instruction execute, operand store
    4. Operand store, operand fetch, instruction fetch, instruction execute, instruction decode
    Answer :     Option ( a )

97. A computer which reduces the symantic gap between the assembly instruction and micro instruction is called as

    1. CISC
    2. RISC .
    3. Harvard
    4. Van-Neuman
    Answer :     Option ( b )

98. A computer which reduces the symantic gap between the High level instruction and micro instruction is called as

    1. CISC
    2. RISC
    3. Harvard
    4. Van-Neuman
    Answer :     Option ( a )

99. identify the correct statement in relation to RISC computer

    1. Large number of register to register instructions
    2. only load and store instructions to access the external memory
    3. shorter instructions
    4. All of the above
    Answer :     Option ( d )

100. The advantage of RISC is that,

     1. Cost efficient
     2. highly reliable
     3. Computing speed
     4. All of the above
     Answer :     Option ( d )

101. Indicate which of the following logic gates can be used to realize all possible combinational Logic functions

     1. OR gates only
     2. NAND gates only
     3. NOR gates only
     4. both b and c
     Answer :     Option ( d )
     Explaination:- NAND and NOR gates can be used to realize all possible combinational logic functions. That is why they are also called Universal gate.

102. The output of a logic gate is ‘1’ when all its input are at logic 0.The gate is either

     1. NAND or an EX OR gate
     2. NOR or an EX-NOR gate
     3. an OR or an EX NOR gate
     4. an AND or an EX-OR gate
     Answer :     Option ( b )
     Explaination:- If we see first gate of the given options then options (c) and (d) are ruled out as OR and AND gates give 0 output for zero inputs. Now see option (a) where NAND gate satisfies the condition but EX-OR gates does not as it gives 0 output for the same inputs. Option (b) is the correct choice where both gates satisfy the given condition.

103. The Boolean function Y= AB + CD is to be realized using only 2 input NAND gates .The minimum number of gates required is

     1. 2
     2. 3
     3. 4
     4. 5
     Answer :     Option ( b )